/***************************************************************************
 *     Copyright (c) 1999-2005, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Mon Mar 28 16:48:45 2005
 *                 MD5 Checksum         ba913b07d554347688609e8e66f4943f
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.006
 *                 Operating System     solaris
 *
 * Spec Versions:  BG                   01
 *                 BVN_MFD              1
 *                 CAP                  1
 *                 DSP_CTRL             03
 *                 IN656                1
 *                 ITFP                 03
 *                 LBG                  1
 *                 NET                  1
 *                 SCL                  1
 *                 VBI_DEC              03
 *                 VD_TOP               5
 *                 VIDEO_DEC            03
 *                 VIP_CTRL             03
 *                 VIP_L2               03
 *                 VPP                  03
 *
 * RDB Files:  /projects/BCM7043/A0/work/gelias/bcm7043_a0/design/chip/rdb/bcm7043_a0.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_top_blockdef.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/cap/rdb/bvn_cap.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/mfd/rdb/bvn_mfd.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/scl/rdb/bvn_scl.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vpp/rdb/vpp.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/video_decoder_top.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_major_revid.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_minor_revid.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656_revid.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/l2/rdb/vip_intr_ctrl2.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vnet/rdb/bvn_net.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/lbg/rdb/vip_lbg.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vib_top.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/video_dec.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vbi_dec.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/itfp/rdb/itfp.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_ctrl.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_top.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_ctrl.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_top.rdb
 *             /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_ctrl.rdb
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCM7043_A0_DSP_REGISTERS_H__
#define BCM7043_A0_DSP_REGISTERS_H__

/***************************************************************************
 *DSP_REGISTERS - DSP Internal
 ***************************************************************************/
#define DSP_REGISTERS_UNIT_EXEC_FLAG             0x005e0000 /* Unit EXEC */
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER       0x005e0004 /* Unit Program Counter */
#define DSP_REGISTERS_DCT_BLOCKS_CBP             0x005e0008 /* Coded Block Pattern */
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF          0x005e000c /* Non Zero Coeff in DCT-0 */
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF          0x005e0010 /* Non Zero Coeff in DCT-1 */
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF          0x005e0014 /* Non Zero Coeff in DCT-2 */
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF          0x005e0018 /* Non Zero Coeff in DCT-3 */
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF          0x005e001c /* Non Zero Coeff in DCT-4 */
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF          0x005e0020 /* Non Zero Coeff in DCT-5 */
#define DSP_REGISTERS_SUM_OF_REGB_DCT0           0x005e0024 /* Summarize DCT-0 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT0           0x005e0028 /* Summarize DCT-0 RC registers */
#define DSP_REGISTERS_SUM_OF_REGB_DCT1           0x005e002c /* Summarize DCT-1 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT1           0x005e0030 /* Summarize DCT-1 RC registers */
#define DSP_REGISTERS_SUM_OF_REGB_DCT2           0x005e0034 /* Summarize DCT-2 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT2           0x005e0038 /* Summarize DCT-2 RC registers */
#define DSP_REGISTERS_SUM_OF_REGB_DCT3           0x005e003c /* Summarize DCT-3 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT3           0x005e0040 /* Summarize DCT-3 RC registers */
#define DSP_REGISTERS_SUM_OF_REGB_DCT4           0x005e0044 /* Summarize DCT-4 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT4           0x005e0048 /* Summarize DCT-4 RC registers */
#define DSP_REGISTERS_SUM_OF_REGB_DCT5           0x005e004c /* Summarize DCT-5 RB registers */
#define DSP_REGISTERS_SUM_OF_REGC_DCT5           0x005e0050 /* Summarize DCT-5 RC registers */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0         0x005e0054 /* MIN MAX Pixel value of DCT-0 */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1         0x005e0058 /* MIN MAX Pixel value of DCT-1 */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2         0x005e005c /* MIN MAX Pixel value of DCT-2 */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3         0x005e0060 /* MIN MAX Pixel value of DCT-3 */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4         0x005e0064 /* MIN MAX Pixel value of DCT-4 */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5         0x005e0068 /* MIN MAX Pixel value of DCT-5 */
#define DSP_REGISTERS_REGISTER_R0                0x005e006c /* REGISTER_R0 - holds ARC calculation to controll DSP operation. */
#define DSP_REGISTERS_LOAD_PARAMETERS_41         0x005e0070 /* DESCRIPTOR1 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_42         0x005e0074 /* DESCRIPTOR2 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_43         0x005e0078 /* DESCRIPTOR3 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_44         0x005e007c /* DESCRIPTOR4 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_45         0x005e0080 /* DESCRIPTOR5 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_INTERRUPT                  0x005e0090 /* DSP INTERRUPTS. */
#define DSP_REGISTERS_MASK_INTERRUPT             0x005e0094 /* DSP MASK INTERRUPTS. */
#define DSP_REGISTERS_LOAD_PARAMETERS_0          0x005e00a0 /* LPAR0 - Loads DSP-Controller with Group 0 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_1          0x005e00b0 /* LPAR1 - Loads DSP-Controller with Group 1 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_2          0x005e00c0 /* LPAR2 - Loads DSP-Controller with Group 2 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_3          0x005e00d0 /* LPAR3 - Loads DSP-Controller with Group 3 Parameters. */
#define DSP_REGISTERS_LOAD_PARAMETERS_4          0x005e00e0 /* LPAR4 - Loads DSP-Controller with Group 4 Parameters. */
#define DSP_REGISTERS_START_UNIT_PC              0x005e00f0 /* START DSP Operation */

/***************************************************************************
 *UNIT_EXEC_FLAG - Unit EXEC
 ***************************************************************************/
/* DSP_REGISTERS :: UNIT_EXEC_FLAG :: reserved0 [31:01] */
#define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_MASK                0xfffffffe
#define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_ALIGN               0
#define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_BITS                31
#define DSP_REGISTERS_UNIT_EXEC_FLAG_reserved0_SHIFT               1

/* DSP_REGISTERS :: UNIT_EXEC_FLAG :: UNIT_EXEC [00:00] */
#define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_MASK                0x00000001
#define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_ALIGN               0
#define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_BITS                1
#define DSP_REGISTERS_UNIT_EXEC_FLAG_UNIT_EXEC_SHIFT               0

/***************************************************************************
 *UNIT_PROGRAM_COUNTER - Unit Program Counter
 ***************************************************************************/
/* DSP_REGISTERS :: UNIT_PROGRAM_COUNTER :: reserved0 [31:09] */
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_MASK          0xfffffe00
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_ALIGN         0
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_BITS          23
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_reserved0_SHIFT         9

/* DSP_REGISTERS :: UNIT_PROGRAM_COUNTER :: UNIT_PC [08:00] */
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_MASK            0x000001ff
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_ALIGN           0
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_BITS            9
#define DSP_REGISTERS_UNIT_PROGRAM_COUNTER_UNIT_PC_SHIFT           0

/***************************************************************************
 *DCT_BLOCKS_CBP - Coded Block Pattern
 ***************************************************************************/
/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: reserved0 [31:06] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_MASK                0xffffffc0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_ALIGN               0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_BITS                26
#define DSP_REGISTERS_DCT_BLOCKS_CBP_reserved0_SHIFT               6

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP5 [05:05] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_MASK                     0x00000020
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP5_SHIFT                    5

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP4 [04:04] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_MASK                     0x00000010
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP4_SHIFT                    4

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP3 [03:03] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_MASK                     0x00000008
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP3_SHIFT                    3

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP2 [02:02] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_MASK                     0x00000004
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP2_SHIFT                    2

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP1 [01:01] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_MASK                     0x00000002
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP1_SHIFT                    1

/* DSP_REGISTERS :: DCT_BLOCKS_CBP :: CBP0 [00:00] */
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_MASK                     0x00000001
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_ALIGN                    0
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_BITS                     1
#define DSP_REGISTERS_DCT_BLOCKS_CBP_CBP0_SHIFT                    0

/***************************************************************************
 *NUM_OF_DCT0_COEFF - Non Zero Coeff in DCT-0
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT0_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT0_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT0_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *NUM_OF_DCT1_COEFF - Non Zero Coeff in DCT-1
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT1_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT1_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT1_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *NUM_OF_DCT2_COEFF - Non Zero Coeff in DCT-2
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT2_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT2_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT2_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *NUM_OF_DCT3_COEFF - Non Zero Coeff in DCT-3
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT3_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT3_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT3_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *NUM_OF_DCT4_COEFF - Non Zero Coeff in DCT-4
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT4_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT4_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT4_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *NUM_OF_DCT5_COEFF - Non Zero Coeff in DCT-5
 ***************************************************************************/
/* DSP_REGISTERS :: NUM_OF_DCT5_COEFF :: reserved0 [31:07] */
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_ALIGN            0
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_BITS             25
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_reserved0_SHIFT            7

/* DSP_REGISTERS :: NUM_OF_DCT5_COEFF :: NUM_OF_COEFF [06:00] */
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_MASK          0x0000007f
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_ALIGN         0
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_BITS          7
#define DSP_REGISTERS_NUM_OF_DCT5_COEFF_NUM_OF_COEFF_SHIFT         0

/***************************************************************************
 *SUM_OF_REGB_DCT0 - Summarize DCT-0 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT0 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT0_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT0 - Summarize DCT-0 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT0 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT0_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *SUM_OF_REGB_DCT1 - Summarize DCT-1 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT1 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT1_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT1 - Summarize DCT-1 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT1 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT1_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *SUM_OF_REGB_DCT2 - Summarize DCT-2 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT2 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT2_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT2 - Summarize DCT-2 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT2 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT2_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *SUM_OF_REGB_DCT3 - Summarize DCT-3 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT3 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT3_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT3 - Summarize DCT-3 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT3 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT3_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *SUM_OF_REGB_DCT4 - Summarize DCT-4 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT4 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT4_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT4 - Summarize DCT-4 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT4 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT4_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *SUM_OF_REGB_DCT5 - Summarize DCT-5 RB registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGB_DCT5 :: SUM_OF_REGB [31:00] */
#define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_BITS            32
#define DSP_REGISTERS_SUM_OF_REGB_DCT5_SUM_OF_REGB_SHIFT           0

/***************************************************************************
 *SUM_OF_REGC_DCT5 - Summarize DCT-5 RC registers
 ***************************************************************************/
/* DSP_REGISTERS :: SUM_OF_REGC_DCT5 :: SUM_OF_REGC [31:00] */
#define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_MASK            0xffffffff
#define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_ALIGN           0
#define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_BITS            32
#define DSP_REGISTERS_SUM_OF_REGC_DCT5_SUM_OF_REGC_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT0 - MIN MAX Pixel value of DCT-0
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT0 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT0_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT1 - MIN MAX Pixel value of DCT-1
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT1 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT1_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT2 - MIN MAX Pixel value of DCT-2
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT2 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT2_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT3 - MIN MAX Pixel value of DCT-3
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT3 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT3_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT4 - MIN MAX Pixel value of DCT-4
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT4 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT4_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *MIN_MAX_PIXEL_DCT5 - MIN MAX Pixel value of DCT-5
 ***************************************************************************/
/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: reserved0 [31:18] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_MASK            0xfffc0000
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_BITS            14
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_reserved0_SHIFT           18

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: MIN_PIXEL [17:09] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_MASK            0x0003fe00
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MIN_PIXEL_SHIFT           9

/* DSP_REGISTERS :: MIN_MAX_PIXEL_DCT5 :: MAX_PIXEL [08:00] */
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_MASK            0x000001ff
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_ALIGN           0
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_BITS            9
#define DSP_REGISTERS_MIN_MAX_PIXEL_DCT5_MAX_PIXEL_SHIFT           0

/***************************************************************************
 *REGISTER_R0 - REGISTER_R0 - holds ARC calculation to controll DSP operation.
 ***************************************************************************/
/* DSP_REGISTERS :: REGISTER_R0 :: REG_R0 [31:00] */
#define DSP_REGISTERS_REGISTER_R0_REG_R0_MASK                      0xffffffff
#define DSP_REGISTERS_REGISTER_R0_REG_R0_ALIGN                     0
#define DSP_REGISTERS_REGISTER_R0_REG_R0_BITS                      32
#define DSP_REGISTERS_REGISTER_R0_REG_R0_SHIFT                     0

/***************************************************************************
 *LOAD_PARAMETERS_41 - DESCRIPTOR1 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_MASK            0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_BITS            7
#define DSP_REGISTERS_LOAD_PARAMETERS_41_reserved0_SHIFT           25

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_MASK       0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_LOAD_NEXT_DESC_SHIFT      24

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_MASK      0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_BITS      6
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_TRANSACTION_SHIFT     18

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_MASK            0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_SHIFT           16
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_NONE            0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_CMB             1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_R_INVR          2
#define DSP_REGISTERS_LOAD_PARAMETERS_41_BUS_WIDTH_Q               3

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_MASK                   0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CR_SHIFT                  15

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_MASK                   0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CB_SHIFT                  14

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_MASK      0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_BITS      1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_RECON_INVR_DATA_SHIFT     13

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_MASK               0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_Q_FLAG_SHIFT              12

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_MASK            0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_INVR_FLAG_SHIFT           11

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_MASK               0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_R_FLAG_SHIFT              10

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_MASK             0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_41_CMB_FLAG_SHIFT            9

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_MASK               0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_BITS               3
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_WA_SHIFT              6

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_MASK             0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_1_SHIFT            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_41 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_MASK             0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_41_MEM_RA_0_SHIFT            0

/***************************************************************************
 *LOAD_PARAMETERS_42 - DESCRIPTOR2 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_MASK            0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_BITS            7
#define DSP_REGISTERS_LOAD_PARAMETERS_42_reserved0_SHIFT           25

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_MASK       0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_LOAD_NEXT_DESC_SHIFT      24

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_MASK      0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_BITS      6
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_TRANSACTION_SHIFT     18

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_MASK            0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_SHIFT           16
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_NONE            0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_CMB             1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_R_INVR          2
#define DSP_REGISTERS_LOAD_PARAMETERS_42_BUS_WIDTH_Q               3

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_MASK                   0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CR_SHIFT                  15

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_MASK                   0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CB_SHIFT                  14

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_MASK      0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_BITS      1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_RECON_INVR_DATA_SHIFT     13

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_MASK               0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_Q_FLAG_SHIFT              12

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_MASK            0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_INVR_FLAG_SHIFT           11

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_MASK               0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_R_FLAG_SHIFT              10

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_MASK             0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_42_CMB_FLAG_SHIFT            9

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_MASK               0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_BITS               3
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_WA_SHIFT              6

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_MASK             0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_1_SHIFT            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_42 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_MASK             0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_42_MEM_RA_0_SHIFT            0

/***************************************************************************
 *LOAD_PARAMETERS_43 - DESCRIPTOR3 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_MASK            0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_BITS            7
#define DSP_REGISTERS_LOAD_PARAMETERS_43_reserved0_SHIFT           25

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_MASK       0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_LOAD_NEXT_DESC_SHIFT      24

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_MASK      0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_BITS      6
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_TRANSACTION_SHIFT     18

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_MASK            0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_SHIFT           16
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_NONE            0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_CMB             1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_R_INVR          2
#define DSP_REGISTERS_LOAD_PARAMETERS_43_BUS_WIDTH_Q               3

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_MASK                   0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CR_SHIFT                  15

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_MASK                   0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CB_SHIFT                  14

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_MASK      0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_BITS      1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_RECON_INVR_DATA_SHIFT     13

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_MASK               0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_Q_FLAG_SHIFT              12

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_MASK            0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_INVR_FLAG_SHIFT           11

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_MASK               0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_R_FLAG_SHIFT              10

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_MASK             0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_43_CMB_FLAG_SHIFT            9

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_MASK               0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_BITS               3
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_WA_SHIFT              6

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_MASK             0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_1_SHIFT            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_43 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_MASK             0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_43_MEM_RA_0_SHIFT            0

/***************************************************************************
 *LOAD_PARAMETERS_44 - DESCRIPTOR4 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_MASK            0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_BITS            7
#define DSP_REGISTERS_LOAD_PARAMETERS_44_reserved0_SHIFT           25

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_MASK       0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_LOAD_NEXT_DESC_SHIFT      24

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_MASK      0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_BITS      6
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_TRANSACTION_SHIFT     18

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_MASK            0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_SHIFT           16
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_NONE            0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_CMB             1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_R_INVR          2
#define DSP_REGISTERS_LOAD_PARAMETERS_44_BUS_WIDTH_Q               3

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_MASK                   0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CR_SHIFT                  15

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_MASK                   0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CB_SHIFT                  14

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_MASK      0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_BITS      1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_RECON_INVR_DATA_SHIFT     13

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_MASK               0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_Q_FLAG_SHIFT              12

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_MASK            0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_INVR_FLAG_SHIFT           11

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_MASK               0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_R_FLAG_SHIFT              10

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_MASK             0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_44_CMB_FLAG_SHIFT            9

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_MASK               0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_BITS               3
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_WA_SHIFT              6

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_MASK             0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_1_SHIFT            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_44 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_MASK             0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_44_MEM_RA_0_SHIFT            0

/***************************************************************************
 *LOAD_PARAMETERS_45 - DESCRIPTOR5 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_MASK            0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_BITS            7
#define DSP_REGISTERS_LOAD_PARAMETERS_45_reserved0_SHIFT           25

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_MASK       0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_LOAD_NEXT_DESC_SHIFT      24

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_MASK      0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_BITS      6
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_TRANSACTION_SHIFT     18

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_MASK            0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_SHIFT           16
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_NONE            0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_CMB             1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_R_INVR          2
#define DSP_REGISTERS_LOAD_PARAMETERS_45_BUS_WIDTH_Q               3

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_MASK                   0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CR_SHIFT                  15

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_MASK                   0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_ALIGN                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_BITS                   1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CB_SHIFT                  14

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_MASK      0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_BITS      1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_RECON_INVR_DATA_SHIFT     13

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_MASK               0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_Q_FLAG_SHIFT              12

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_MASK            0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_INVR_FLAG_SHIFT           11

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_MASK               0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_BITS               1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_R_FLAG_SHIFT              10

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_MASK             0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_45_CMB_FLAG_SHIFT            9

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_MASK               0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_ALIGN              0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_BITS               3
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_WA_SHIFT              6

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_MASK             0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_1_SHIFT            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_45 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_MASK             0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_BITS             3
#define DSP_REGISTERS_LOAD_PARAMETERS_45_MEM_RA_0_SHIFT            0

/***************************************************************************
 *INTERRUPT - DSP INTERRUPTS.
 ***************************************************************************/
/* DSP_REGISTERS :: INTERRUPT :: reserved0 [31:08] */
#define DSP_REGISTERS_INTERRUPT_reserved0_MASK                     0xffffff00
#define DSP_REGISTERS_INTERRUPT_reserved0_ALIGN                    0
#define DSP_REGISTERS_INTERRUPT_reserved0_BITS                     24
#define DSP_REGISTERS_INTERRUPT_reserved0_SHIFT                    8

/* DSP_REGISTERS :: INTERRUPT :: ERROR_MCROM_ADD [07:07] */
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_MASK               0x00000080
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_ALIGN              0
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_BITS               1
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ADD_SHIFT              7

/* DSP_REGISTERS :: INTERRUPT :: ERROR_MCROM_ACK [06:06] */
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_MASK               0x00000040
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_ALIGN              0
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_BITS               1
#define DSP_REGISTERS_INTERRUPT_ERROR_MCROM_ACK_SHIFT              6

/* DSP_REGISTERS :: INTERRUPT :: ERROR_CROM_ADD [05:05] */
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_MASK                0x00000020
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_ALIGN               0
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_BITS                1
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ADD_SHIFT               5

/* DSP_REGISTERS :: INTERRUPT :: ERROR_CROM_ACK [04:04] */
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_MASK                0x00000010
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_ALIGN               0
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_BITS                1
#define DSP_REGISTERS_INTERRUPT_ERROR_CROM_ACK_SHIFT               4

/* DSP_REGISTERS :: INTERRUPT :: ERROR_BANK_ADD [03:03] */
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_MASK                0x00000008
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_ALIGN               0
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_BITS                1
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ADD_SHIFT               3

/* DSP_REGISTERS :: INTERRUPT :: ERROR_BANK_ACK [02:02] */
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_MASK                0x00000004
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_ALIGN               0
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_BITS                1
#define DSP_REGISTERS_INTERRUPT_ERROR_BANK_ACK_SHIFT               2

/* DSP_REGISTERS :: INTERRUPT :: BANK_ERROR [01:01] */
#define DSP_REGISTERS_INTERRUPT_BANK_ERROR_MASK                    0x00000002
#define DSP_REGISTERS_INTERRUPT_BANK_ERROR_ALIGN                   0
#define DSP_REGISTERS_INTERRUPT_BANK_ERROR_BITS                    1
#define DSP_REGISTERS_INTERRUPT_BANK_ERROR_SHIFT                   1

/* DSP_REGISTERS :: INTERRUPT :: EXEC [00:00] */
#define DSP_REGISTERS_INTERRUPT_EXEC_MASK                          0x00000001
#define DSP_REGISTERS_INTERRUPT_EXEC_ALIGN                         0
#define DSP_REGISTERS_INTERRUPT_EXEC_BITS                          1
#define DSP_REGISTERS_INTERRUPT_EXEC_SHIFT                         0

/***************************************************************************
 *MASK_INTERRUPT - DSP MASK INTERRUPTS.
 ***************************************************************************/
/* DSP_REGISTERS :: MASK_INTERRUPT :: reserved0 [31:08] */
#define DSP_REGISTERS_MASK_INTERRUPT_reserved0_MASK                0xffffff00
#define DSP_REGISTERS_MASK_INTERRUPT_reserved0_ALIGN               0
#define DSP_REGISTERS_MASK_INTERRUPT_reserved0_BITS                24
#define DSP_REGISTERS_MASK_INTERRUPT_reserved0_SHIFT               8

/* DSP_REGISTERS :: MASK_INTERRUPT :: MASK [07:00] */
#define DSP_REGISTERS_MASK_INTERRUPT_MASK_MASK                     0x000000ff
#define DSP_REGISTERS_MASK_INTERRUPT_MASK_ALIGN                    0
#define DSP_REGISTERS_MASK_INTERRUPT_MASK_BITS                     8
#define DSP_REGISTERS_MASK_INTERRUPT_MASK_SHIFT                    0

/***************************************************************************
 *LOAD_PARAMETERS_0 - LPAR0 - Loads DSP-Controller with Group 0 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: reserved0 [31:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_MASK             0xffffc000
#define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_BITS             18
#define DSP_REGISTERS_LOAD_PARAMETERS_0_reserved0_SHIFT            14

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: CHOOSE_CLIP_PAIR [13:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_MASK      0x00003000
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_ALIGN     0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_BITS      2
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_SHIFT     12
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_0 0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_1 1
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_2 2
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CHOOSE_CLIP_PAIR_CLIP_PAIR_3 3

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: CLIP [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_MASK                  0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_ALIGN                 0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_BITS                  1
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_SHIFT                 11
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_PIXEL_CLIP            0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_CLIP_CLIP                  1

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_WA [10:08] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_MASK                0x00000700
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_BITS                3
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_WA_SHIFT               8

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: INC_MEM_RA [07:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_MASK            0x000000c0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_BITS            2
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_SHIFT           6
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_NO_INC          0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_ONE_INC         1
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_TWO_INC         2
#define DSP_REGISTERS_LOAD_PARAMETERS_0_INC_MEM_RA_FIELD_INC       3

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_MASK              0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_BITS              3
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_1_SHIFT             3

/* DSP_REGISTERS :: LOAD_PARAMETERS_0 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_MASK              0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_BITS              3
#define DSP_REGISTERS_LOAD_PARAMETERS_0_MEM_RA_0_SHIFT             0

/***************************************************************************
 *LOAD_PARAMETERS_1 - LPAR1 - Loads DSP-Controller with Group 1 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: reserved0 [31:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_MASK             0xfffff000
#define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_BITS             20
#define DSP_REGISTERS_LOAD_PARAMETERS_1_reserved0_SHIFT            12

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: REGA_MUX [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_MASK              0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_BITS              1
#define DSP_REGISTERS_LOAD_PARAMETERS_1_REGA_MUX_SHIFT             11

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: INC_MEM_WA [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_MASK            0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_SHIFT           10
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_ONE_INC         0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_INC_MEM_WA_FIELD_INC       1

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: FIELD [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_MASK                 0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_ALIGN                0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_BITS                 1
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_SHIFT                9
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_DIS                  0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_FIELD_FIELD_MODE           1

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: CROM_INC [08:08] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_MASK              0x00000100
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_BITS              1
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CROM_INC_SHIFT             8

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: IQUANT [07:07] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_MASK                0x00000080
#define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_BITS                1
#define DSP_REGISTERS_LOAD_PARAMETERS_1_IQUANT_SHIFT               7

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: ROUND_REG_LEFT_SCALE [06:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_MASK  0x00000078
#define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_ALIGN 0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_BITS  4
#define DSP_REGISTERS_LOAD_PARAMETERS_1_ROUND_REG_LEFT_SCALE_SHIFT 3

/* DSP_REGISTERS :: LOAD_PARAMETERS_1 :: CHOOSE_ROUND_QUARTET [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_MASK  0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_ALIGN 0
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_BITS  3
#define DSP_REGISTERS_LOAD_PARAMETERS_1_CHOOSE_ROUND_QUARTET_SHIFT 0

/***************************************************************************
 *LOAD_PARAMETERS_2 - LPAR2 - Loads DSP-Controller with Group 2 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: reserved0 [31:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_MASK             0xfffff000
#define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_BITS             20
#define DSP_REGISTERS_LOAD_PARAMETERS_2_reserved0_SHIFT            12

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: REGISTER_TYPE [11:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_MASK         0x00000c00
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_ALIGN        0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_BITS         2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_TYPE_SHIFT        10

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: REGISTER_GROUP [09:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_MASK        0x000003c0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_ALIGN       0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_BITS        4
#define DSP_REGISTERS_LOAD_PARAMETERS_2_REGISTER_GROUP_SHIFT       6

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: LOAD [05:04] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_MASK                  0x00000030
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_ALIGN                 0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_BITS                  2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_SHIFT                 4
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_DIS              0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_LUMA_CHROMA_SCALER 1
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_CLIP             2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_LOAD_LOAD_ROUND_COEFF      3

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: CBP_CONT [03:02] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_MASK              0x0000000c
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_BITS              2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_SHIFT             2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_REGULAR_CBP       0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_DC_CBP         1
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_FIRST_LINE_COL_CBP 2
#define DSP_REGISTERS_LOAD_PARAMETERS_2_CBP_CONT_NO_CBP            3

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: MPEG4 [01:01] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_MASK                 0x00000002
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_ALIGN                0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_BITS                 1
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG4_SHIFT                1

/* DSP_REGISTERS :: LOAD_PARAMETERS_2 :: MPEG1 [00:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_MASK                 0x00000001
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_ALIGN                0
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_BITS                 1
#define DSP_REGISTERS_LOAD_PARAMETERS_2_MPEG1_SHIFT                0

/***************************************************************************
 *LOAD_PARAMETERS_3 - LPAR3 - Loads DSP-Controller with Group 3 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: reserved0 [31:07] */
#define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_MASK             0xffffff80
#define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_BITS             25
#define DSP_REGISTERS_LOAD_PARAMETERS_3_reserved0_SHIFT            7

/* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: MEM_WA [06:01] */
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_MASK                0x0000007e
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_BITS                6
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_WA_SHIFT               1

/* DSP_REGISTERS :: LOAD_PARAMETERS_3 :: MEM_RA_SEL [00:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_MASK            0x00000001
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_ALIGN           0
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_BITS            1
#define DSP_REGISTERS_LOAD_PARAMETERS_3_MEM_RA_SEL_SHIFT           0

/***************************************************************************
 *LOAD_PARAMETERS_4 - LPAR4 - Loads DSP-Controller with Group 4 Parameters.
 ***************************************************************************/
/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: reserved0 [31:25] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_MASK             0xfe000000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_BITS             7
#define DSP_REGISTERS_LOAD_PARAMETERS_4_reserved0_SHIFT            25

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: LOAD_NEXT_DESC [24:24] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_MASK        0x01000000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_ALIGN       0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_BITS        1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_LOAD_NEXT_DESC_SHIFT       24

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: BUS_TRANSACTION [23:18] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_MASK       0x00fc0000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_BITS       6
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_TRANSACTION_SHIFT      18

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: BUS_WIDTH [17:16] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_MASK             0x00030000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_BITS             2
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_SHIFT            16
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_NONE             0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_CMB              1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_R_INVR           2
#define DSP_REGISTERS_LOAD_PARAMETERS_4_BUS_WIDTH_Q                3

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CR [15:15] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_MASK                    0x00008000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_ALIGN                   0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_BITS                    1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CR_SHIFT                   15

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CB [14:14] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_MASK                    0x00004000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_ALIGN                   0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_BITS                    1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CB_SHIFT                   14

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: RECON_INVR_DATA [13:13] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_MASK       0x00002000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_ALIGN      0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_BITS       1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_RECON_INVR_DATA_SHIFT      13

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: Q_FLAG [12:12] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_MASK                0x00001000
#define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_BITS                1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_Q_FLAG_SHIFT               12

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: INVR_FLAG [11:11] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_MASK             0x00000800
#define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_ALIGN            0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_BITS             1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_INVR_FLAG_SHIFT            11

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: R_FLAG [10:10] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_MASK                0x00000400
#define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_BITS                1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_R_FLAG_SHIFT               10

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: CMB_FLAG [09:09] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_MASK              0x00000200
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_BITS              1
#define DSP_REGISTERS_LOAD_PARAMETERS_4_CMB_FLAG_SHIFT             9

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_WA [08:06] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_MASK                0x000001c0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_ALIGN               0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_BITS                3
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_WA_SHIFT               6

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_RA_1 [05:03] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_MASK              0x00000038
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_BITS              3
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_1_SHIFT             3

/* DSP_REGISTERS :: LOAD_PARAMETERS_4 :: MEM_RA_0 [02:00] */
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_MASK              0x00000007
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_ALIGN             0
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_BITS              3
#define DSP_REGISTERS_LOAD_PARAMETERS_4_MEM_RA_0_SHIFT             0

/***************************************************************************
 *START_UNIT_PC - START DSP Operation
 ***************************************************************************/
/* DSP_REGISTERS :: START_UNIT_PC :: reserved0 [31:09] */
#define DSP_REGISTERS_START_UNIT_PC_reserved0_MASK                 0xfffffe00
#define DSP_REGISTERS_START_UNIT_PC_reserved0_ALIGN                0
#define DSP_REGISTERS_START_UNIT_PC_reserved0_BITS                 23
#define DSP_REGISTERS_START_UNIT_PC_reserved0_SHIFT                9

/* DSP_REGISTERS :: START_UNIT_PC :: PROGRAM_COUNTER [08:00] */
#define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_MASK           0x000001ff
#define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_ALIGN          0
#define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_BITS           9
#define DSP_REGISTERS_START_UNIT_PC_PROGRAM_COUNTER_SHIFT          0

#endif /* #ifndef BCM7043_A0_DSP_REGISTERS_H__ */

/* End of File */
